The invention concerns a phase control circuit (PLL=Phase locked loop) and a special digitally controlled oscillator. Known types of phase control circuits are described for instance in the journal "Funkschau" 6/83 pp 61-68 and 7/83 pp 69, 70.
Digitally controlled oscillators are oscillators in which the frequency is determined by a digital input variable. Such oscillators consist chiefly of a frequency control circuit and are known in various versions (synthesizers).
Particularly high demands are required of phase control circuits which process signals subject to timing errors. In order to remove the timing error it is necessary both to produce clock frequencies which follow the timing error of the signal as closely as possible and also those which do not follow the timing error, and thus form the constant time base for removal of the timing error.
Timing errors are generated in recording devices. The timing errors are measurable with the aid of periodic signals which are recorded alongside the actual information signal. The video signal on a PCM signal contains periodic signals in the form of the synchronization signal or clock signal. For non-periodic analog signals, e.g. audio signals, the recording of an additional pilot frequency is required.
Known types of video recording devices are video disc and video tape recorders. The timing errors of the signals reproduced by these devices possess a particularly strong component with a period corresponding to the rotation period of the read head or the disc. For video signals with a 50 Hz vertical frequency which is common in many home video tape recorders, the period of the timing error is 40 ms. The timing error is 40 ms because in addition to the 50 Hz timing error caused by the head switching, there is also 25 Hz timing error caused by the head adjustment tolerances. With video discs, the timing error caused by eccentricity has a period of 40 or 80 ms, depending on whether 2 or 4 fields are scanned per revolution.
For the measurement and for the removal of timing errors two timing signals are always required. The first timing signal follows the timing error as closely as possible whereas the second timing signal is maintained as free from error as possible, i.e. constant. On the average, both signals must have the same frequency or maintain a fixed frequency ratio, so that e.g. a buffer store used for timing error removal does not overflow.
The first timing signal is obtained by using the timing signal contained in the signal after separation directly or after error removal using a PLL circuit with a low time constant.
The second timing signal is obtained by using a PLL circuit with a very large time constant. The time constant or the low pass filter in the control circuit of the PLL should therefore suppress to a large extent the fundamental frequency of the control voltage obtained with the aid of the phase comparator stage (25 or 12.5 Hz).
The realization of a PLL circuit which suppresses to a sufficient extent such low frequency timing fluctuations has been simplified by the method presented in Federal Republic of Germany Offenlegungsschift DE-OS No. 27 45 375, published Apr. 19, 1979. According to this method, only short sections of the timing signal subject to timing error are used for the generation of the control voltage in the phase comparator stage, and the time separation of these sections correspond to the period of the timing fluctuations. As a result of this method, the voltage trace at the output of the phase comparator stage is already free of the effects of the timing fluctuations. A substantially reduced time constant is sufficient for the smoothing of the control voltage which is still required. The delay time reduction in the control loop associated with this is to the advantage of the stability of the PLL circuit.
Advances in the digitalization of signal processing allow the introduction of new signal transmission methods. An example of this is the serial transmission of time compressed color signal components as timeplex or MAC signals. Signal stores which can hold a sample consisting of one line are required for time compression and expansion.
It was proposed in Federal Republic of Germany Patent Application No. 33 45 142 that these stores be used at the same time for timing error removal. Thus for instance, the signal derived from a currently available VTR can be transformed into a timing error free timeplex signal. The timing error of the video recorder is particularly difficult because of its sawtooth shape. The lines in which head switching occurs can be significantly too short or too long. The task of error removal consists in so distributing these fluctuations over all the lines of a complete picture that all lines including those in which there is head switching are of the same length.
The effecting of the time compression according to P No. 33 45 142 involves reading the signal which is affected by timing errors into the line store using a first clock which follows the timing fluctuations of the signal as closely as possible. The reading out is then effected using a second clock frequency which is as near as possible constant, and is likewise generated from the signal with the timing errors using a PLL circuit. The ratio between the frequencies of the first and second clock frequencies which correspond to the degree of compression must be exactly maintained on average, so that overflow of the line store is avoided.
The PLL circuit given in DE-OS No. 27 45 375 facilitates the production of the second clock frequency, but this circuit requires a means of filtering in the control voltage generation path. The delay in the control circuit associated with this has a deleterious effect on the stability of the circuit. Because of the long intervals between measurements in the phase comparison stage the tendency towards phase oscillations is particularly great. The poor lock-in behavior requires special measures for providing the right operating condition.